RISC-V IoT Security Approach Could Change Processor Market

The RISC-V instruction set architecture could become a dominant processor for IoT applications, according to a cybersecurity executive.

Courtney Bjorlin

January 16, 2019

3 Min Read
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Securing IoT devices requires innovation at the processor level, a space RISC-V, a free and open Instruction Set Architecture (ISA) for processors, is uniquely poised to fill, according to the CEO and founder of Dover Microsystems.

One of the biggest unmet IoT security needs is protecting processors from being taken over when there’s a software vulnerability, according to Dover Microsystems’ Jothy Rosenberg. Being able to make the processor immune to network-based attacks is not something within the normal litany of security technologies, he said.

Instead of relying only on compartmentalization and communication security, RISC-V is unique in that it includes computing security to stop buffer overflows and protect the processor from being overtaken by cyberattacks that arrive via the network and exploit vulnerabilities in the code. Estimates of the latter are as high as 50 bugs per 1,000 lines of source code, he said, citing stats from the widely known software development book Code Complete.

“If we get RISC-V security right, it will become the dominant processor in the IoT market that could be half a trillion dollars,” Rosenberg said at last month’s inaugural RISC-V Summit held in Santa Clara, which drew more than 1,100 people. “RISC-V is beginning to hit its stride right as the IoT is really reaching that level of explosion. That’s going to create an enormous opportunity for us.”

The RISC-V ISA, with roots in academia and research, is now shepherded by a collaboration of more than 100 members of the RISC-V Foundation launched in 2015, including founding members like Qualcomm and NXP.

RISC-V’s major advantages include its low barriers to entry and lack of legacy requirements to support, according to Rosenberg. A RISC-V core can be protected from network-based attacks using three innovations, according to Rosenberg. Metadata generated about the intent of the application provides a “co-processor” with information. Then, a set of rules called micropolicies is applied to describe the security properties to enforce. And a hardware mechanism watches the instructions, examines the metadata, and puts it all together to block instructions that would bring harm.

Rosenberg described his company’s IP solution, CoreGuard, to that end. It integrates with existing processors, and includes metadata and micropolicies that ensure that the right software instructions are processed.

The RISC-V community, according to Rosenberg, is ideally suited use the technology to create processors to help secure IoT devices.

“The many eyes, many hands of an open source community are going to create a safer IoT and enable its growth,” he said.  “This will cement RISC-V as the processor for the half trillion dollar IoT market, and at the same time it will fundamentally change the change the processor industry forever.”

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