IBM Chip Process to Extend Moore's Law, Propel IoT AdoptionIBM Chip Process to Extend Moore's Law, Propel IoT Adoption
New process for 5-nanometer chip will yield smaller, faster, more efficient processors that reinstate Moore's Law and prove useful for IoT, AI, AR/VR and blockchain.
June 5, 2017
IBM and Research Alliance partners Samsung and GlobalFoundaries have developed a process to build a 5-nanometer chip, the company announced today, an advancement that’s expected to extend Moore’s Law in its advancement toward smaller and denser microprocessors. The chip fabrication technology also has the potential to further lower barriers to IoT adoption.
The potential for new uses of computing in IoT, artificial intelligence (AI), augmented reality/virtual reality (AR/VR) and blockchain all depend on smaller, faster, and more efficient chips, said analyst Ray Wang via an email interview. Wang is founder of Constellation Research, a Silicon Valley firm that advises Global 2000 companies on the future, business strategy, and disruptive technology adoption. While the IBM chip process is at least three years away from a commercially viable chip, the breakthrough is important, as planners and designers will be anticipating this capability.
“Silicon nanosheets at 5 nanometers would have been unimaginable just three years ago,” Wang said. “This new process helps organizations imagine new possibilities in computing, especially applications that use very little power and are extremely mobile, such as AR/VR inside biomedical devices, omnipresent cognitive applications, and even more precision in IoT.”
The announcement was made at the 2017 Symposia on VLSI Technology and Circuits, being held in Kyoto, Japan, this week. The scientists involved on the IBM chip research were working as part of the IBM-led Research Alliance at SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, N.Y.
Compared with the leading-edge 10-nanometer technology available in the market, a nanosheet-based 5-nanometer technology can deliver 40% performance enhancement at fixed power, or 75% power savings at matched performance, according to the IBM announcement. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices before needing to be charged. On a mobile phone with 10 percent battery life, 5-nanometer chips would lend hours, not minutes, of power before needing to recharge, for instance.
The development hinged on changing how the elements of the chip were arranged and the materials used, according to an IBM blog detailing the announcement from Huiming Bu, director of Silicon Integration and Device Research. The team stacked layers of silicon nanosheets together horizontally as the device structure of the transistor, instead of the standard FinFET architecture.
“The change from today’s vertical architecture to horizontal layers of silicon opened a fourth ‘gate’ on the transistor that enabled electrical signals to pass through and between other transistors on a chip,” Bu wrote. “At these dimensions, it means that those signals are passing through a switch that’s no larger than the width of two to three DNA strands, side by side.”
The new IBM chip design will have significant potential in consumer electronics and software first, but presents enormous opportunities as the technology is applied in healthcare, security and retail, Wang said.
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